SEQUENCE BREAK SYSTEM

An optional in-out control is available for PDP-3. This control, termed

the Sequence Break System, allows concurrent operation of several in-out

devices and the main sequence. The system has, nominally, 16 automatic

interrupt channels arranged in a priority chain.

A break to a particular sequence may be initiated by the completion of

an in-out device, the program, or an external signal. If this sequence

has priority, the C(AC), C(IO), C(PC), and C(IA) are stored in three

fixed memory locations unique to that sequence. Since the C(PC) and

C(IA) are eighteen bits each, these two registers are stored in one

memory location. The next instruction is taken from a fourth location.

This instruction is usually a jump to a suitable routine. The program is

now operating in the new sequence. This new sequence may be broken by a

higher priority sequence. A typical program loop for handling an in-out

sequence would contain 3 to 5 instructions, including the appropriate

iot. These are followed by load AD and load IO from the fixed locations

and a special indirect jump through the location of the previous C(PC).

This special jump also loads the IA. This last instruction terminates

the sequence.

Preliminary Specifications: Programmed Data Processor Model Three (PDP-3) October, 1960 · 第 56 / 71 题