This group of instructions will rotate or shift the Accumulator and/or
the In-Out Register. When the two registers operate combined, the In-Out
Register is considered to be a 36 bit magnitude extension of the right
end of the Accumulator.
Rotate is a non-arithmetic cyclic shift. That is, the two ends of the
register are logically tied together and information is rotated as
though the register were a ring.
Shift is an arithmetic operation and is in effect multiplication of the
number in the register by 2^{+N}, where N is the number of shifts. Shift
or rotate instructions involving more than 33 steps can be used for
simulating time delays. 36 rotate steps of the Accumulator will return
all information to its original position.
_Rotate Accumulator Right_ (13 usec. maximum for 36 shifts)
rar N Operation Code 671
This instruction will rotate the bits of the Accumulator right N
positions, where N is octal digits 7-11 of the instructions word.
_Rotate Accumulator Left_ (13 usec. maximum for 36 shifts)
ral N Operation Code 661
This instruction will rotate the bits of the Accumulator left N
Positions, where N is octal digits 7-11 of the instruction word.
_Shift Accumulator Right_ (13 usec. maximum for 36 shifts)
sar N Operation Code 675
This instruction will shift the contents of the Accumulator right N
positions, where N is octal digits 7-11 of the instruction word.
_Shift Accumulator Left_ (13 usec. maximum for 36 shifts)
sal N Operation Code 665
This instruction will shift the contents of the Accumulator left N
positions, where N is octal digits 7-11 of the instruction word.
_Rotate In-Out Register Right_ (13 usec. maximum for 36 shifts)
rir N Operation Code 672
This instruction will rotate the bits of the In-Out Register right N
positions, where N is octal digits 7-11 of the instruction word.
_Rotate In-Out Register Left_ (13 usec. maximum for 36 shifts)
ril N Operation Code 662
This instruction will rotate the bits of the In-Out Register left N
positions, where N is octal digits 7-11 of the instruction word.
_Shift In-Out Register Right_ (13 usec. maximum for 36 shifts)
sir N Operation Code 676
This instruction will shift the contents of the In-Out Register right N
positions, where N is octal digits 7-11 of the instruction word.
_Shift In-Out Register Left_ (13 usec. maximum for 36 shifts)
sil N Operation Code 666
This instruction will shift the contents of the In-Out Register left N
positions, where N is octal digits 7-11 of the instruction word.
_Rotate AC and IO Right_ (13 usec. maximum for 36 shifts)
rcr N Operation Code 673
This instruction will rotate the bits of the combined register right in
a single ring N positions, where N is octal digits 7-11 of the
instruction word.
_Rotate AC and IO Left_ (13 usec. maximum for 36 shifts)
rcl N Operation Code 663
This instruction will rotate the bits of the combined register left in a
single ring N position, where N is octal digits 7-11 of the instruction
word.
_Shift AC and IO Right_ (13 usec. maximum for 36 shifts)
scr N Operation Code 677
This instruction will shift the contents of the combined register right
N positions, where N is octal digits 7-11 of the instruction word.
_Shift AC and IO Left_ (13 usec. maximum for 36 shifts)
scl N Operation Code 667
This instruction will shift the contents of the combined registers left
N positions, where N is octal digits 7-11 of the instruction word.
* * * * *
_Skip Group_ (5 usec.)
skp Y Operation Code 64
This group of instructions senses the state of various flip-flops and
switches in the machine. It does not require any reference to memory.
The address portion of the instruction selects the particular function
to be sensed. All members of this group have the same operation code.
_Skip on ZERO Accumulator_ (5 usec.)
sza Address 100
If the Accumulator is equal to plus ZERO (all bits are ZERO) the Program
Counter is advanced one extra position and the next instruction in the
sequence is skipped.
_Skip on Plus Accumulator_ (5 usec.)
spa Address 200
If the sign bit of the Accumulator is ZERO, the Program Counter is
advanced one extra position and the next instruction in the sequence is
skipped.
_Skip on Minus Accumulator_ (5 usec.)
sma Address 400
If the sign bit of the Accumulator is ONE, the Program Counter is
advanced one extra position and the next instruction in the sequence is
skipped.
_Skip on ZERO Overflow_ (5 usec.)
szo Address 1000
If the overflow flip-flop is a ZERO the Program Counter is advanced one
extra position and the next instruction in the sequence will be skipped.
The overflow flip-flop is cleared by this instruction. This flip-flop is
set by addition, subtraction, or division that exceeds the capacity of
the Accumulator. The overflow flip-flop is not cleared by arithmetic
operations which do not cause an overflow. Thus, a whole series of
arithmetic operations may be checked for correctness by a single szo.
The overflow flip-flop is cleared by the "Start" Switch.
_Skip on Plus In-Out Register_ (5 usec.)
spi Address 2000
If the sign digit of the In-Out Register is ZERO the Program Counter is
indexed one extra position and the next instruction in the sequence is
skipped.
_Skip on ZERO Switch_ (5 usec.)
szs Addresses 10, 20, ... 70
If the selected Sense Switch is ZERO, the Program Counter is advanced
one extra position and the next instruction in the sequence will be
skipped. Address 10 senses the position of Sense Switch 1, Address 20
Switch 2, etc. Address 70 senses all the switches. If 70 is selected all
6 switches must be ZERO to cause the skip to occur.
_Skip on ZERO Program Flag_ (5 usec.)
szf Addresses 0 to 7 inclusive
If the selected program flag is a ZERO, the Program Counter is advanced
one extra position and the next instruction in the sequence will be
skipped. Address 0 is no selection. Address 1 selects program flag one,
etc. Address 7 selects all programs flags. All flags must be ZERO to
cause the skip.
The instructions in the One Cycle Skip group may be combined to form the
inclusive OR of the separate skips. Thus, if address 3000 is selected,
the skip would occur if the overflow flip-flop equals ZERO or if the
In-Out Register is positive. The combined instruction would still take 5
microseconds.
* * * * *
_Operate Group_ (5 usec.)
opr Y Operation Code 76
This instruction group performs miscellaneous operations on various
Central Processor Registers. The address portion of the instruction
specifies the action to be performed.
_Clear In-Out Register_ (5 usec.)
cli Address equal 4000
This instruction clears the In-Out Register.
_Load Accumulator from Test Word_ (5 usec.)
lat Address 2000
This instruction forms the inclusive OR of the C(AC) and the contents of
the Test Word. This instruction is usually combined with address 200
(clear Accumulator), so that C(AC) will equal the contents of the Test
Word Switches.
_Complement Accumulator_ (5 usec.)
cma Address 1000
This instruction complements (makes negative) the contents of the
Accumulator.
_Halt_
hlt Address 400
This instruction stops the computer.
_Clear Accumulator_ (5 usec.)
cla Address 200
This instruction clears (sets equal to plus 0) the contents of the
Accumulator.
_Clear Selected Program Flag_ (5 usec.)
clf Address 01 to 07 inclusive
The selected program flag will be cleared. Address 00 selects no program
flag, 01 clears program flag 1, 02 clears program flag 2, etc. Address
07 clears all program flags.
_Set Selected Program Flag_ (5 usec.)
stf Address 11 to 17 inclusive
* * * * *
_In-Out Transfer Group_ (5 usec. without in-out wait)
iot x Y Operation Code 72
The variations within this group of instructions perform all the in-out
control and information transfer functions. If bit six (normally the
Indirect Address bit) is a ONE, the computer will halt and wait for the
completion pulse from the device activated. When this device delivers
its completion, the computer will resume operation of the instruction
sequence.
An incidental fact which may be of importance in certain scientific or
real time control applications is that the time origin of operations
following an in-out completion pulse is identical with the time of that
pulse.
Most in-out operations require a known minimum time before completion.
This time may be utilized for programming. The appropriate In-Out
Transfer is given with no in-out wait (bit six a ZERO). The instruction
sequence then continues. This sequence must include an iot instruction
which performs nothing but the in-out wait. This last instruction must
occur before the safe minimum time. A table of minimum times for all
in-out devices is delivered with the computer. It lists minimum time
before completion pulse and minimum In-Out Register free time.
The details of the In-Out Transfer variations are listed under
Input-Output.
The mnemonic codes and addresses for the standard equipment are:
_Read Paper Tape Alphanumeric Mode_
rpa Address 1
_Read Paper Tape Binary Mode_
rpb Address 2
_Typewriter Output_
tyo Address 3
_Typewriter Input_
tyi Address 4
_Punch Paper Tape Alphanumeric Mode_
ppa Address 5
_Punch Paper Tape Binary Mode_
ppb Address 6