Non-Indexable Memory Instructions

These instructions have the same word format as the indexable

instructions. Since they operate on the index register location, x, they

cannot be indexed.

_Skip on Negative index_ (10 usec.)

snx x Y Operation Code 46

The number in octal digits 7 through 11 of the instruction word is added

to the C(x). This addition is done in the 15 bit Index Adder using 1's

complement arithmetic. If, after the addition, the sum is negative, the

Program Counter is advanced one extra position and the next instruction

in the sequence is skipped. The contents of octal digits 0-5 of the

index register location are unaffected by this instruction.

_Skip on Positive index_ (10 usec.)

spx x Y Operation Code 44

The number in octal digits 7 through 11 of the instruction word is added

to the C(x). This addition is done in the 15 bit Index Adder using 1's

complement arithmetic.

If, after the addition, the sum is positive, the Program Counter is

advanced one extra position and the next instruction in the sequence is

skipped. The contents of octal digits 0-5 of the index register location

are unaffected by this instruction.

_Load Index Register_ (10 usec.)

lir x Y Operation Code 14

The octal digits 7 through 11 (Y) of the instruction will replace the

corresponding digits of the memory register specified by x. Octal digit

6 of the memory register will be left clear. Digits 0-5 of the memory

register are unchanged.

_Deposit Index Adder_ (10 usec.)

dia x Y Operation Code 16

The C(IA) replace the octal digits 7 through 11 of memory location Y.

Octal digit 6 of Y is cleared. Digits 0 through 5 of Y are left

unchanged. The x portion of the instruction is ignored.

Preliminary Specifications: Programmed Data Processor Model Three (PDP-3) October, 1960 · 第 44 / 71 题